Updated : January 25th; Input amplifier
Updated : January 26th; Audio filter
A couple of days ago I found the circuit of 20m DC PSK31 receiver at the website of va3iul. The website of va3iul is probably well known in the radio amateur community. It features 100’s of circuit design ideas on all kind of topics related to RF design : oscillators, noise sources, filters, phase shifters, it is all there.
Now my google search came up with an image of a 20m PSK31 receiver designed by DG2XK hosted by va3iul. it didn’t state in which magazine it was originally published and it did not show the component values.
Now the fact that it did not show the component values piqued my interest. Could I redesign this receiver based on the circuit diagram alone and could I change it to my favorite band 40m?
Design or redesign?
Gain distribution
To get from a 1µV input signal to 1V output signal is 6 orders of magnitude or 120 dB. The NE612 has a gain of 17dB typical (14 dB minimum). If we assume the audio power amplifier (not shown) has a gain of 20 dB (10x). The FET source follower will have a gain of circa 0.7x = – 3dB. That means we still need to “find” (or design-in, if you find that more posh) 80 dB of gain.
If we design the passive input LC network to have a voltage gain of 20 dB, we need about 30 dB for each of the two AF gain stages. If we choose R3 = R4 = 4k7 and R7 and R6 = 220k we get a gain of 33 dB. If we choose R10 = 4k7 and R12 = 220k, we also get a gain of 33 dB. In total 66 dB so we have about 6 dB spare gain.
You will notice a couple of differences with regards to the original schematic:
-the 78L08 was replaced with a 78L05 for I did not have the former at hand
– the input band pass filter was not mounted for now
– the audio low-pass filter was skipped
– SA612AN pin 2 was connected to ground as per the datasheet
Gain measurement and verification
The next step was to measure the actual gain of the current set-up. To prevent input saturation an additional input attenuator was added (see schematic below). This have an additional 26 dB of attenuation.
The signals were generated with a Siglent SDG1032X dual waveform generator. Channel 1 (RF input) was set to 7.000 Mhz 10mVpp @ 50 ohm load. Channel 2 (VFO) was set to 7.001 Mhz 300mVpp again @ 50 Ohm load. The receiver output was measured with a 100 Mhz oscilloscope. The voltage at A2.2 was measured to be 7 Vpp. This translates to a gain of 57 dB. Add to this the additional input attenuation of 26 dB = 83 dB of total gain. This is about 3dB less than the back of the envelope calculated 86 dB.
Now there are a couple of ‘buts’: the gain of the input JFET was estimated to be – 3dB and was in no way properly calculated. This would be quit difficult for the spread in characteristics between individual JFETs can be quit large.
Secondly, the SA612 has a typical gain of 17 dB with a minimum of 14 dB gain, again a spread of 3dB. Last but not least, we ignored the loading of the input resistance of opamp A1 on the output of the SA612 mixer IC. The output resistance of the SA612 is roughly 1.5 k ohm. The input resistance for the non-inverting input of A1 is 4k7 + 220k. This is so large that the loading on the previous circuit can safely be ignored. The input resistance for the inverting input is maximum 4k7 (actually a bit less). This 4k7 is placed in parallel with the 1k5 output resistance of the SA612 for a total resistance of 1137 Ohm. The gain will be 1137/1500 times lower, this equals to -2.4 dB.
| Input Buffer | SA612 | A1 | A2 | Total |
| – 3 dB | 17 dB (typ.) – 2.4 dB = 14.6 dB | 39 dB | 33 dB | 83.6 dB |
Note on capacitors and audio filtering
In a DC receiver much of the signal selectivity is generated by AF filtering. So it is good to have a look at that. The first low-pas filter is formed by capacitor C11 and C13 together with the 1.5 kΩ collector out resistance. With the current values 10nF (C11 and C13) and 1.5 kΩ, this causes a corner frequency fc of 10.6 kHz. (The circuit diagram above shows 1nF which I installed erroneously initially ).
C12 and C14 in series with R3 and R4 respectively form a high pass filter with a -3 dB frequency fc of 340 Hz.
C17 (100p) in parallel with R7 (220 kΩ) form another low pass filter with a cut-off frequency of 7.2 kHz.
Finally there will be a passive low-pass filter which will have a cut-off frequency of circa 3.3 kHz (will be implemented in a next update).
Input amplifier
The current input amplifier is a JFET configured as source follower. Although easy to setup and build it features a typical gain of ca 0.7x. That might not seem much but this also increases the noise figure. To measure the actual gain of the current setup the schematic in the next figure was used:
The input attenuator was left in place from the previous measurement. In series with the JFET’s source and the spectrum analyzer input a 1.5 kΩ. was added. This resistor simulates the load of the NE612 input impedance. Together with the 50 Ω input impedance this form a -30 dB attenuator. The tracking generator in the spectrum analyzer (output uncalibrated) is set to 0 dBm output. The signal at the SA is then measured to be -58.7 dBm. The gain of the source-follower is thus -2.7 dBm.
Next an PNP transistor was added to the JFET to change the configuration to a compound-series feedback buffer with wide-band unity gain. This configuration was already featured in AN-32 “FET Circuit Applications” by National semiconductor in 1970! See next diagram.
The rest of the measurement set-up was left unchanged and in place. Now the output was measured to be -56.8 dBm. This translates to a gain of -0.5 dBm or a gain of 0.94 x.
Audio filter
The current filter in the design is a so-called M-derived low-pass filter. It is a rather old filter topology. It has all but been replaced by the Cauer topology (see diagram). It features an additional filter capacitor at the input. The resulting filter has steeper roll off after the cut-off frequency. You can think of the input resistance R1 and the additional input capacitor as additional RC low pass filter.
For the actual filter, I wanted to have a corner frequency fc of circa 3.3 kHz, an impedance of 2 kΩ and a minimum attenuation in the stop band of 40 dB. Oh, and I wanted to use an inductor of 68 mH (this was all I had available). A lot of requirements! Luckily enough, Elsie managed to design a filter with not too exotic capacitor values.
The end result is a -3 dB point of 3.2 kHz and an attenuation of > 61dB at 7.5Khz. A whopping 54 dB in just over 4.3 kHz! Not too shabby for such a simple filter!
Literature
- AN-32 : ‘FET Circuit Applications‘ by National Semiconductor (now Texas Instruments)
- James L. Tonne W4ENE has written many useful programs. You can find Elsie on his website
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