JFET testing

For an upcoming RF amplifier project I needed a couple of JFETs. The spread in device characteristics is quit broad. For the BF256B Vp ranges from -0.5 to -8.0V ( a factor 16! ) and IDSS ranges from 6 mA to 13 mA. Since, I bought a small stock of them, I decided to satisfy my curiosity and measure to static device characteristics.

To measure Vp and IDSS a small test circuit was build on a piece of perf. board. If the switch SW1 is open, VP is measured. A very small current will flow (typically somewhere between 1 uA and 10uA), which will create a small voltage drop over R1, which is almost equal to VP. If the switch is closed, there will be almost a short-circuit between gate-source and hence you will measure the IDSS. “Almost” because there is still a small voltage over resistor R2.

The internal resistance of the Digital Volt Meter must be quit high for accurate measurement of VP. Most DVMs do have an internal resistance of 10 MOhm or higher. So this should be no problem. For R2 a resistor with 5% tolerance is used.

For all the different JFET there are only 6 (3! = 6) possible pin-outs

Possible JFET pin-outs

Off all these options, number 1 and 6 are the same but mirrored, so are #2 and #4, as well as #3 and #5. So, in the end only the 1st three options are truly unique. To implement this, either a triple three-way socket can be used or a single 5-way socket. Because of ease of wiring the latter option was chosen, of which the pin-out is : D-G-S-D-G. For test-socket a 5-way female pin header was used.

A summary of the measurement data can be found below. The datasheet with all the measurements can be downloaded from the download section.

VP [ V ]IDSS [ mA ]

It is interesting to see, that although the spread in device characteristics as indicated by the datasheet is quit broad, in real life (and from a single batch) it is much smaller.

Vp vs Idss for 25 pieces BF256B (1 batch)

In the graph above VP is plotted vs. IDSS. It is interesting to see that all the measurements are almost on a single line. The slope of which is circa 220 ohm (VP,max – VP,min)/ (IDSS,max– IDSS,min) . Also there is a positive correlation between VP and IDSS.

Abstract N-channel JFET model

This probably makes sense, when the abstract N-channel model is taken into account. If the N-layer is slightly thicker, the resistance will be lower and hence IDSS will be larger. However, the voltage applied to the gate also needs to be more negative to create an electric field that is strong enough to go into cut-off mode.

Measurement data [Open Document Spreadsheet .ods]

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